Electrostatic discharge (ESD) is a continuing problem in the design, manufacture, and utilization of integrated circuits (ICs). A voltage vs time plot of a typical ESD event 100 is shown in FIG. 1. The voltage (and/or current) rises very rapidly, and falls quickly thereafter. An integrated circuit may include an ESD protection shunting component, such as an ESD protection field effect transistor (FET), connected between an input/output (I/O) pad and a reference node, for example a Vss or ground node, of the integrated circuit. The integrated circuit may further include an ESD detection circuit with a “sense” functionality coupled to the I/O pad and with a “signal out” functionality which sends a signal to a latch of the integrated circuit when an ESD event occurs. The latch may have a “gate bias” functionality which maintains an on-state gate bias at a gate node of the ESD protection FET while the ESD detection circuit signals that the ESD event is occurring. The latch may provide efficient shunting of the I/O pad to the reference node by providing a constant on-state gate bias regardless of a varying strength of the signal from the ESD detection circuit.
A problem arises when the ESD detection circuit is triggered by a voltage excursion when the integrated circuit is coupled to a power supply for normal operation. A voltage vs time plot of such a voltage excursion 102, also known as an electrical overstress (EOS) event 102, and ensuing power application 104 is also shown in FIG. 1. The EOS event 102 causes the ESD detection circuit to initiate the signal to the latch to provide the on-state bias to the ESD protection FET. The application of power 104 to the integrated circuit causes the ESD detection circuit to maintain the signal to the latch which then maintains the ESD protection FET in an on state. Thus, the ESD protection FET may be undesirably left on during normal operation of the integrated circuit, possibly disadvantageously leading to failure of the ESD protection FET and possibly to failure of the integrated circuit. EOS events as described above may occur when the power supply of a laptop or cell phone is plugged into a socket before it is plugged into the laptop of cell phone.
The risetime of the voltage excursion 102 can be slower than the risetime of the ESD event 100, as depicted in FIG. 1. Currently, circuits that trigger the ESD detection circuit with very fast rise times but do not trigger with less fast rise times are being used to avoid latching the ESD protection FET gate during an EOS event, with partial success. However, these solutions are not immune to triggering under EOS events with faster risetimes which trigger the ESD detection circuit.